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| MITSUBISHI SEMICONDUCTOR PS51259-A PS51259-A TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE PS51259-A INTEGRATED POWER FUNCTIONS * Single phase AC input, DC output IGBT/FWD converter bridge * 600V, 20Arms (Input current) INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS * IGBTS driver circuit * Control supply under-voltage (UV) protection * Input interface : 5~15V line CMOS/TTL compatible, Schmitt Trigger receiver circuit (Active high) APPLICATION AC100~200V Active-Converter for PFC (Power Factor Correction), of Air-conditioner and so on. Fig. 1 PACKAGE OUTLINES Dimensions in mm 27x2.8(=75.6) 2.80.3 B TERMINAL CODE 1 2 3 4 5 6 7 8 9 10 11 12 13 N2 N2 NC NC NC NC NC NC NC NC NC NC NC 14 15 16 17 18 19 20 21 22 23 24 25 26 GND VD VIN GND NC NC NC NC P S R N N 21.40.5 12 34 56 78 9 10 11 12 13 14 15 16 17 18 19 20 21 Type name , Lot No. 11.50.5 310.5 2 .5 -4 0 .2 22 23 24 25 26 13.40.5 8 100.3 100.3 100.3 670.3 0.6 200.3 0.8 1.4 A Detail A 1.8 2 790.5 21 TERMINAL 80.5 161 9. 10. 11 TERMINAL (71) Heat sink Detail B 280.5 Mar. 2003 MITSUBISHI SEMICONDUCTOR PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) MAIN CIRCUIT PART Symbol Vi Vi(surge) VO VO(surge) VCES VRRM Ii Ii(125%) I2t Tj Parameter Supply Voltage Supply Voltage (surge) Output Voltage Output Voltage (surge) Collector-Emitter Voltage Repetitive Peak Reverse Voltage Input Current (100% Load) Input Current (125% Load) for Fu sing Junction Temperature I2t Conditions Applied between : S-R Applied between : S-R, Surge value, Non-operating Applied between : P-N Applied between : P-N, Surge value, Non-operating -- -- TC +90C, Vi = 200V, VO = 300V, fPWM = 20kHz TC +90C, Vi = 200V, VO = 300V, fPWM = 20kHz, 1 min Non-repetitive Value for 1msec of Surge Current (Note 1) Ratings 264 500 450 500 600 600 20 25 120 -20~+125 Unit Vrms V V V V V Arms Arms A 2s C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-PFC is 150C (@ TC 100C) however, to ensure safe operation of the DIP-PFC, the average junction temperature should be limited to Tj(ave) 125C (@ TC 100C). CONTROL (PROTECTION) PART Symbol VD VIN Parameter Control supply voltage Control input voltage Condition Applied between : VD-GND Applied between : VIN-GND Ratings 20 0~VD+0.5 Unit V V TOTAL SYSTEM Symbol TC Tstg Viso Parameter Module case operation temperature Storage temperature Isolation voltage Condition (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Ratings -20~+100 -40~+125 1500 Unit C C Vrms Note 2 : TC MEASUREMENT POINT Control Terminals Heat sink Tc Tc Power Terminals Heat sink boundary Mar. 2003 MITSUBISHI SEMICONDUCTOR PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f) Parameter Junction to case thermal resistance Contact thermal resistance Inverter IGBT part Inverter FWDi part Case to fin, (per 1 module) thermal grease applied Condition Min. -- -- -- Limits Typ. -- -- -- Max. 1.55 1.90 0.067 Unit C/W C/W C/W ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VF ton trr tc(on) toff tc(off) ICES IR Irr Parameter Collector-emitter saturation voltage Forward voltage Condition VD = 15V, VIN = 5V, IC = 50A IF = 50A VCC = 300V, VD = 15V IC = 30A, Tj = 125C, VIN = 5V 0V Inductive load VCE = 600V VR = 600V Tj = 25C Tj = 125C Tj = 25C Tj = 125C Min. -- -- -- -- -- -- -- -- -- -- -- -- Limits Typ. 1.8 2.1 0.29 0.13 0.15 0.46 0.17 -- -- -- -- 13 Max. 2.4 2.6 -- -- -- -- -- 1 10 1 10 -- Unit V V s s s s s mA mA A Switching times Collector-emitter cut-off current Reverse current FWDi reverse recovery current VCC = 300V, VD = 15V, IC = 30A, Tj = 25C CONTROL (PROTECTION) PART Symbol VD ID IIN Vth(on) Vth(off) UVDt UVDr Parameter Control supply voltage Circuit current Control input current ON threshold voltage OFF threshold voltage Supply circuit under-voltage protection Condition Applied between : VD-GND Applied between : VD = 15V, VIN = 5V VD-GND VD = 15V, VIN = 0V VD = 15V, VIN = 5V Applied between : VIN-GND Tj 125C Trip level Reset level Limits Min. 13.5 -- -- -- -- 1.3 10.3 10.8 Typ. 15.0 0.8 0.7 0.3 3.0 2.0 -- -- Max. 16.5 3.0 3.0 0.45 3.7 -- 12.5 13.0 Unit V mA mA V V V V Mar. 2003 MITSUBISHI SEMICONDUCTOR PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Symbol -- -- -- Parameter Mounting torque Weight Heat-sink flatness Mounting screw : M4 (Note 3) Condition Limits Min. 0.98 -- -50 Typ. 1.18 54 -- Max. 1.47 -- 100 Unit N*m g m Note 3: Measurement point of heat-sink flatness Measurement point +- 3mm Heat sink - + Place to contact a heat sink Heat sink RECOMMENDED OPERATION CONDITIONS Symbol Vi VD VD fPWM VIN(on) VIN(off) Parameter Supply voltage Control supply voltage Control supply variation PWM input frequency Input ON threshold voltage Input OFF threshold voltage Condition Applied between : S-R Applied between : VD-GND TC 100C, Tj 125C Applied between : VIN-GND Min. 90 13.5 -1 -- Limits Typ. -- 15.0 -- 20 4.0~VD 0~1.0 Max. 264 16.5 1 -- Unit Vrms V V/s kHz V V Mar. 2003 MITSUBISHI SEMICONDUCTOR PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 THE DIP-PFC INTERNAL CIRCUIT DIP-PFC P R S LVIC VD VCC ROUT VIN VIN N2 SOUT GND GND VNO N Mar. 2003 MITSUBISHI SEMICONDUCTOR PS51259-A TRANSFER-MOLD TYPE INSULATED TYPE DIP-PFC Wiring Guidelines Because DIP-PFC switches large current at a very high speed, considerable large surge voltage is generated easily between P and N terminals. Please pay attention to the following items: * The area of P-Co-N shown in Fig. 3 should be as small as possible because the rectangle shaped switching current flows on this route. In addition, please add a bypass condenser Co' with good frequency response such as a polypropylene film condenser closely to the P and N terminals. * The two IGBT emitters are connected to the VNO terminal of LVIC inside the DIP-PFC. If the internal wiring inductance shown as L1 and L2 in Fig. 4 is too large, large surge voltage will be generated by di/dt. Especially, the lower the temperature, the faster the switching speed, therefore the larger the di/dt. This surge voltage applies to the VNO and N terminals, which is possible to destruct LVIC. * In order to suppress the surge voltage, the external wiring method shown in Fig. 4 is recommended. To reduce the parasitic wiring inductance, the wiring of the external terminals of N(N-1) and N(N-2) should be made as short as possible. * Please mount a fast clamp diode (EG01Y@Sanken) between N and control GND terminals to prevent control GND potential variation from the minus voltage of N terminal. Fig. 3 DIP-PFC INTERFACE DIP * PFC P R N/F S Co' VD LVIC GND VNO VIN N (N-1, N-2) N2 + Co MCU Control IC Fig. 4 RECOMMENDED WIRING METHOD N2 N2 P + S R L2 N-1 To restrain the IPM surge voltage, mount the condenser closely to the terminals To reduce the parasitic inductance, this wire should close to N terminal Insert a diode here N-2 L1 GND VD VIN GND + VD Control input Mar. 2003 |
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